This relates generally to integrated circuit packages, and more particularly, to integrated circuit packages with more than one integrated circuit die.
An integrated circuit package typically includes an integrated circuit die and a substrate on which the die is mounted. The die can be coupled to the substrate through bonding wires or solder bumps. Signals from the integrated circuit die may then travel through the bonding wires or solder bumps to the substrate.
As demands on integrated circuit technology continue to outstrip even the gains afforded by ever decreasing device dimensions, more and more applications demand a packaged solution with more integration than possible in one silicon die. In an effort to meet this need, more than one die may be placed within a single integrated circuit package (i.e., a multichip package). As different types of devices cater to different types of applications, more dies may be required in some systems to meet the requirements of high performance applications. Accordingly, to obtain better performance and higher density, an integrated circuit package may include multiple dies arranged laterally along the same plane or may include multiple dies stacked on top of one another.
For example, an application-specific integrated circuit (ASIC) die and an accompanying memory die may be mounted on a common interposer substrate. An interface block may be included for facilitating communications between the ASIC die and the memory die. This interface block is, however, configured to only support the communications protocol associated with that particular memory die. While this may provide optimal performance for this particular configuration, the interface block is incapable of supporting communications with a wide variety of different memory dies and other types of daughter dies.
It is within this context that the embodiments described herein arise.